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- MEXT
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- Function
- memory management
- 01AMD's testing showed that it could run timing checks with half the DRAM capacity while retaining 95% of performance compared to a full DRAM setup.
- 02TrendForce projected a 10% to 15% rise in conventional DRAM contract prices in Q4 2026 due to supply shortages.
- 03AMD's MEXT software allows for moving infrequently accessed data to flash storage, effectively expanding memory capacity and reducing costs.
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- 04By implementing MEXT across 145 servers, AMD avoided $4.9 million in DRAM purchases and achieved an 83% cost reduction compared to an all-DRAM upgrade.
- 05AMD plans to expand the MEXT rollout to 2,000 servers in 2027, enhancing memory capacity for its IT infrastructure.
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A chip is nearly ready for manufacturing when an engineer changes the layout to fix a timing issue. The team has to rerun its checks before signing off. If other jobs are already tying up server memory, the team can add capacity or queue the checks.
Adding capacity is getting more expensive. With dynamic random-access memory (DRAM) in short supply, TrendForce projected that conventional DRAM contract prices would rise 10% to 15% quarter over quarter in Q4 2026. At Team Group’s latest investor briefing, CEO Gerry Chen said the company turned to the spot market when contracted volumes fell short, with spot prices running 30% to 50% above contract prices.
At AMD In Depth, Derek Dicker, who leads AMD’s enterprise EPYC business, described how the company’s IT and silicon design teams tested a way to run timing checks with less DRAM. They ran Synopsys PrimeTime on a sixth-generation EPYC server with 256 GB of DRAM and 256 GB of capacity backed by flash storage. The setup retained 95% of the performance of a 512 GB all-DRAM system.
What AMD Moved to Flash
PrimeTime checks whether signals can travel through a chip design within the time allowed. A timing check can occupy hundreds of gigabytes of memory, though some of that data may go untouched for much of the run.
AMD’s MEXT software moves infrequently accessed data to flash and predicts which data the application will need again soon. It moves that data back into DRAM ahead of demand. When a job needs data that is still on flash, retrieving it takes longer.
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In a separate PrimeTime test on Microsoft Azure, AMD used MEXT to expand effective memory capacity from 1.4 TB to 2.6 TB. The extra capacity let more jobs start at once. The same four jobs finished in 6.6 hours, down from 9.3 hours.
What AMD IT Saved Across 145 Servers
AMD used MEXT to expand memory capacity across an initial 145 servers in its own IT infrastructure. The company said it avoided $4.9 million in DRAM purchases and estimated that the memory expansion cost 83% less than an equivalent all-DRAM upgrade, based on a price of $15,500 per 256 GB memory module. AMD plans to expand the rollout to 2,000 servers in 2027.
AMD did not disclose how many of those servers ran chip-design workloads. For engineering teams weighing a similar upgrade, the cost per completed check depends on the price of the flash and software, as well as how many jobs the servers can finish.
Where Faster Memory Still Pays
In a separate briefing, AMD IT said functional verification, which checks whether a circuit behaves as intended, accounts for the largest share of its chip-design computing demand. For the simulation workload it discussed, AMD reported roughly 40% shorter runtimes with its existing 3D V-Cache processors. The larger on-chip cache gave the processor faster access to data it needed repeatedly.
In the PrimeTime test, AMD found room to move some data farther from the processor and halve the server’s DRAM. “And the most that they lost in performance was five percent,” Dicker said.
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