Manufacturing
Deployment record
In the tracker →- Organisation
- Samsung Electronics
- System
- NVIDIA PhysicsNeMo
- Stage
- Live
- Function
- thermal simulation
- Built on
- NVIDIA
- 01Samsung Electronics reduced chip thermal simulation time from 18 hours to 41 seconds using a GPU and a coarser grid.
- 02The new simulation method involves splitting the semiconductor structure into smaller regions to better calculate heat and mechanical stress.
- 03Archgen Labs developed AI tools that predict temperature maps for 3D chips in an average of 62 milliseconds, achieving a 5,000-fold speedup over traditional methods.
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- 04Samsung plans to expand the use of digital twins in semiconductor manufacturing to improve efficiency and production scheduling.
- 05Archgen is collaborating with GlobalFoundries on 3D chip development and aims for its first tapeout in mid-2027.
Samsung Electronics
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A chip designer moves a block closer to memory to shorten the path data has to travel. The move can improve signal timing, but it can also concentrate heat. If the thermal simulation runs overnight, the designer may have to wait until morning to find out whether the new layout created a hot spot.
At NVIDIA’s AI Day Seoul, Samsung Electronics showed how much shorter that wait could be. In one test, a chip thermal simulation that took about 18 hours on a 32-core processor finished in 41 seconds.
Lee Seong-yeop of Samsung Electronics’ Semiconductor Division said smaller devices and more complex manufacturing processes had made heat- and stress-related defects a priority. Samsung split the semiconductor structure into smaller regions, calculated how heat and mechanical stress behaved in each, then combined the results. Lee said Samsung developed an algorithm to reduce errors where those regions meet.
For the 41-second run, the team used NVIDIA PhysicsNeMo to estimate material properties and ran the calculation on a graphics processing unit (GPU) with a coarser grid. The 18-hour baseline used a finer grid.
Checking for Hot Spots While the Layout Can Still Change
The trade-off becomes more pressing in stacked chips, where placing components on adjacent layers can shorten connections and make heat harder to remove.
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Founded in 2026 by Hariharan Ayappane and Naveen Venkat, Archgen Labs is a San Francisco startup backed by Y Combinator. It builds AI tools that help engineers decide what goes on each layer of a 3D chip and assess how those choices affect signal timing and heat.
“When those checks take too long, teams explore fewer designs,” Ayappane and Venkat wrote. In Archgen’s benchmark, its LayerTherm model predicted a temperature map in 62 milliseconds on average, compared with 314 seconds for conventional electronic design automation (EDA) solvers. The startup reported a roughly 5,000-fold speedup.
Samsung timed a coarse-grid simulation on a GPU. Archgen timed a model’s prediction of a temperature map. The disclosures leave open how reliably either approach catches hot spots in unfamiliar designs.
Archgen said it has signed pilot projects and is working with GlobalFoundries on 3D chip development. It is targeting its first tapeout, when the design is handed off for fabrication, in mid-2027. The pilots give Archgen a chance to see whether earlier heat checks mean fewer layouts get sent back for revision after detailed verification.
From the Chip Layout to the Fab
Samsung also plans to expand its use of digital twins across semiconductor manufacturing, while SK hynix is developing virtual models of its fabs with NVIDIA. A fab team could use a model to see whether rerouting materials would clear a bottleneck or move the queue to another machine before changing the production schedule.
Back at the design desk, the next benchmark for Samsung is how many layouts engineers can take through thermal review in a day, including the ones that still need a fine-grid simulation.
